The invention relates to an output stage comprising an input terminal for receiving an input signal; an output terminal for delivering an output signal in response to the input signal; a first and a second supply terminal for receiving a supply voltage; a field effect transistor comprising a gate, and a main current path between a source and a drain coupled between the first supply terminal and the output terminal; and slewing control means for reducing the speed of voltage change at the gate of the field effect transistor for reducing the speed of current change through the main current path of the field effect transistor when the output signal changes from a first steady state via a transition area to a second steady state.
Such an output stage is known from U.S. Pat. No. 5,013,940. In this known output stage the slewing control means limit the discharge current from the gate-source capacitance of the field effect transistor when the field effect transistor is turning off because the output signal changes from the second (logic "low") steady state via the transition area to the first (logic "high") steady state. This is done to limit the rate of change of current through the first supply terminal and thus also limit the rate of change of current through the output terminal. The limitation of the rate of change through the first supply terminal and/or the output terminal is needed to reduce parasitic voltage spikes at the first supply terminal and/or at the output terminal caused by parasitic inductances in series with the first input terminal and/or in series with the output terminal.
When in the known output stage the field effect transistor is turning on because the output signal changes from the first (logic "high") steady state via the transition area to the second (logic "low") steady state, the field effect transistor will be switched off quite abruptly somewhere during the transition area because the field effect transistor is no longer in saturation due to a lack of drain-source voltage of the field effect transistor. This has a drawback of causing relatively large voltage spikes at the first supply terminal and/or the output terminal.